In many known methods for manufacturing semiconductor chips, a relatively large wafer, for example, of silicon is used as a starting material. Such wafers can be obtained by slicing a crystal ingot to a suitable thickness to obtain a number of nearly disk-shaped semiconductor wafers. Typically, both surfaces of each wafer are subjected to abrasive machining, followed by etching in a suitable mixed acid solution, after which one surface of each wafer is polished to obtain a mirror surface. Circuits are applied to the mirror surface of the resulting semiconductor wafer by known processing steps of printing, etching, diffusion, doping, etc.
In the methods described above, the silicon wafers are sliced from the crystal ingot to a thickness that is greater than desirable for a finished integrated circuit product so as to provide a more robust wafer to stand up to the rigors of the integrated circuit fabrication processes. Particularly, relatively thick silicon wafers are necessary during the integrated circuit fabrication steps to prevent warpage and breakage of the wafer as a result of certain heating, handling and other circuit fabrication processes. After the integrated circuits have been fabricated, it is desirable to reduce the thickness of the wafer in order to reduce the overall size and mass of the finished product.
U.S. Pat. No. 5,223,734 discloses a gettering process for semiconductor manufacturing. The gettering process is performed after device formation and after a protective layer such as borophosphorus silicate glass (BPSG) or phosphorous silicate glass (PSG) has been applied to the front side of a semiconductor wafer. The gettering process includes thinning and roughening a backside of the wafer using chemical mechanical planarization (CMP), depositing and diffusing a gettering agent such as phosphorus into the backside of the wafer. The wafer can then be annealed for driving in the gettering agent and segregating mobile contaminants in the wafer at gettering centers formed at the dislocations and at gettering agent sites within the wafer crystal structure. The annealing step may also function to reflow and planarize the BPSG or PSG protective layer. As optional steps, the front side of the wafer may be chemically mechanically planarized (CMP) to planarize the protective, BPSG layer, prior to depositing and diffusing the gettering agent into the backside of the wafer. Additionally, as another optional step, the front side of the wafer may be chemically mechanically planarized (CMP) after the annealing step, if required, to further planarize the protective (BPSG) layer.
U.S. Pat. No. 5,851,845 (Farnworth) discloses a method for packaging a semiconductor die. The package includes a thinned die mounted on a compliant adhesive layer to a substrate. The package is formed by providing a wafer containing a plurality of dice, thinning a backside of the wafer by etching or polishing, attaching the thinned wafer to the substrate, and then dicing the wafer. Either a wet or dry etching process can be used to etch the backside of the wafer.
U.S. Pat. No. 5,895,972 discloses thinning a silicon semiconductor substrate by etching, polishing, milling, etc.
Despite these and other efforts, there remains a need for techniques which enable the manufacture of products with ever-increasing degrees of precision, and with ever-decreasing size, without sacrificing or compromising required properties.